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Assessment> DLDFinal-192 (1). United International University CSE 1325: Department of Computer Science and Engineering CSE 225: DIGITAL LOGIC DESIGN,.

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Department of Computer Science and Engineering CSE 225: DIGITAL LOGIC DESIGN, Final Summer 2019 Total Marks: 40 Duration: 2 hour Section A: Answer both of the Questions, 1 and 2. 2. Using D fli ... p-flops, design a sequence recognizer that can recognize the sequence, “0110”. You have to show (a) state diagram, (b) the flip-flops’ input table, (c) equations and (d) the logic diagram. [2x4] Section B: Answer any two of the Questions from 3, 4 and 5. 3. (a) Implement a 3-to-8 decoder using two 2-to-4 decoders and a single NOT gate. Label the decoder pin names and their inputs/outputs carefully. (b) Consider a digital system with four binary bits as input and a single bit as output. The binary output is 1 if the number of 1s in the input is less than the number of 0s, otherwise the output is 0. Implement this system using a 8x1 MUX and a single NOT gate only. [Show More]

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