Computer Architecture > Research Paper > University of Texas, Arlington - CS 6304project-1 Cache levels Unified caches (All)
University of Texas, Arlington - CS 6304project-1 Cache levels Unified caches
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EE/CE/CS 6304: Computer Architecture Project #1 Prof. Yiorgos Makris September 17, 2015 ______________________________________________________________________________ Project #1 (Report due at ins ... tructor’s office or in class by end of lecture on Thursday, October 15th, 2015) Project description: Cache design choices (i.e. # of levels, size, associativity, replacement policy etc.) affect the performance of a microprocessor. In this project, you are asked to fine-tune the cache hierarchy of an Alpha microprocessor for 4 individual benchmarks. The cache design parameters you can modify are: - Cache levels: One or two levels, for data and instruction caches. - Unified caches: Selection of separate vs. unified instruction/data caches. For example, you can have separate L1 caches and a unified L2 cache. - Size: Cache size, one of the most important choices. - Associativity: Selection of cache associativity (e.g. direct mapped, 2-way set associative, etc.). - Block size: Block size of the cache, usually 64 or 32 bytes. - Block replacement policy: Selection between FIFO, LRU and Random [Show More]
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