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Iowa State University CPR E 281 mcarryme27

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Synchronous Sequential Circuits Assigned: Week 12 Due Date: Nov. 12, 2018 1 This is the key. P1 (20 points): We want to design a circuit with input W and an output Z, where Z will equal 1 if, fo ... r the last three clock cycles, W has been 1. A: Draw a state diagram for a Moore Finite State Machine (FSM) that implements this circuit in four states, specified as follows: B: Complete a state table for the above state diagram with the state assignments as shown below for state variables D1 and D0. W=0 W=1 Z S-0 : 00 S-0 : 00 S-I : 01 0 S-I : 01 S-0 : 00 S-II : 10 0 S-II : 10 S-0 : 00 S-III : 11 0 S-III : 11 S-0 : 00 S-III : 11 1 C: Use K-maps to show that the output and next-state variables can be expressed as: D: Let’s consider if the states were encoded as: S-0 = 00, S-I = 01, S-II = 11, S-III = 10 This study source was downloaded by 100000824368823 from CourseHero.com on 11-12-2022 21:49:51 GMT -06:00 https://www.coursehero.com/file/72285473/HW10-Sample-Solutionspdf/ Cpr E 281 HW10 ELECTRICAL AND COMPUTER ENGINEERING IOWA STATE UNIVERSITY Synchronous Sequential Circuits Assigned: Week 12 Due Date: Nov. 12, 2018 2 Use K-maps to show that the output and next-state variables with this new encoding can be expressed as: E: Draw the circuit for this FSM (developed in part D) using only DFFs, AND gates, and one OR gate (Do not use any NOT gates). [Show More]

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