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Engineering & Technology Electrical Engineering Q1 a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded...

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Question below questions only 18474592 Image transcriptions Q1 a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by ... a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.) (Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.) Part DigClock Part List OFFTIME = .5US DSTM1 Filestim ONTIME = .5US CLK US FideShim16 DELAY = STARTVAL = 0 FileStim4 OPPVAL = 1 FileStimB IAL Libraries D X Design Cache EVAL SOURCE b) Read the specification of 74LS47 (BCD-to-7-Segment Decoder shown in Appendix) to see how the logic IC operates to drive a 7-segment LED display. Draw the circuit connection of the decade counter in (a) and the decoder to display the count value on the 7-segment LED display. Further explain why common anode configuration is needed for our 7-segment display rather than the common cathode configuration. 1/6 IDC 480(189) 0,80(031) PIN 9.10( 36) 1400.551) 2.541-100) So(.295) (21.101043) 8.50(.335) 0.25(010)- 3,00.130 MIN. 5.081.200) BS-A32 RD BS-C32ARD 1.6 1.6 92 Design a 2-digit decade counter that counts from 00 to 59 and repeats. Use two cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. . (Define the simulation timings for at least one full counting cycle from 0 to 59 and back to 0.) [Show More]

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